A PSRAM functions as a static random access memory (SRAM) based on an architecture of a dynamic random access memory (DRAM). Traditionally, two different word lines of a DRAM active at the same time are inhibited. In addition to writing and reading, a DRAM has to be refreshed periodically to avoid the event of data loss. However, the refresh operation has to activate another word line, so the timings of reading, writing and refreshing has to be differentiated from each other to prevent the conflict of two word lines active simultaneously.
As shown in FIG. 1, the timings of reading, writing and refreshing are determined by an address transition detection signal ATD. The ATD signal switches to a high level whenever an address transition occurs, e.g., from address N−1 to address N, or from address N to address N+1. The ATD signal remains at a high level for a time period TRC—D, namely cycle time or operation time of the DRAM, and then switches to a low level. While the ATD signal is at the low level, the word line of the address is active, i.e., at the high level, for being written and read. On the contrary, while the ATD signal is at the high level, the word line is deactivated for refresh operation.
Under the SRAM operation, an address cannot be identified to perform reading, writing or refreshing when the address is at a ready state, and the active time of a word line, normally equivalent to the TRC—D, is limited, so as to prevent the refresh operation from being hindered. However, the above-mentioned operation has several drawbacks. For instance, if a refresh signal is generated after a reading signal, and a writing signal is generated after a refresh operation is done, because the word line has to be off before refreshing, the word line has to be reactivated for writing. Accordingly, current consumption is significantly increased.